Thin film transistors (TFT) can be divided into a polysilicon (P-Si) TFT and an amorphous silicon (a-Si) TFT, and the difference between the two lies in different transistor characteristics. As the a-Si per se has characteristics of low on-state current (Ion), low mobility and poor stability, its applications in many fields are restricted. An electron mobility of the P-Si is faster than that of the a-Si with a disorder arrangement by 200-300 times. P-Si products mainly comprise a high temperature polysilicon (HTPS) product and a lower temperature polysilicon (LTPS) product.
An LTPS technology is a new generation of TFT display fabrication technology, by which an a-Si thin film layer is transferred to a P-Si thin film layer using an excimer laser anneal (ELA), a metal induced crystallization (MIC) or a solid phase crystallization (SPC). An LTPS TFT display has a faster response time and a higher resolution and thus has a better image display quality. Using the LTPS technology during forming a peripheral circuit of a display device can reduce the number of integrated circuits (IC), simplify a periphery of the display device and thus, a narrow frame technology is achieved.
A traditional LTPS TFT array substrate comprises: a glass substrate, a buffer layer, a channel region, a gate insulating layer, a gate electrode, a source/drain electrode, an interlayer insulating layer, a passivation layer, a pixel electrode layer and a pixel electrode insulating protective layer (PDL) (this layer is applicable to an LTPS Active Matrix/Organic Light Emitting Diode (AMOLED), while an LTPS liquid crystal display (LCD) may not have this layer). The fabricating process of the traditional LTPS TFT array substrate is a 7-Mask process, specifically comprising:
The first mask process: forming a polysilicon of a source/drain region and a channel region of a TFT.
First, a buffer layer of SiNx/SiO2 is formed on a glass substrate, then a layer of an a-Si thin film is deposited on the buffer layer, and the a-Si thin film is transformed into a P-Si thin film through an LIPS crystallization manner (such as, ELA, MIC and SPC). Then, a layer of photoresist is coated on the P-Si thin film, exposing, developing, etching, removing of the photoresist are performed by using a first mask, and thus, a channel region pattern is formed.
The second mask process: forming a gate electrode and a gate line pattern.
A gate insulating layer and a gate metal layer thin film are deposited on patterns formed by the first mask process, and the gate insulating layer thin film can be formed of SiNx/SiO2. Then a photoresist is coated on the gate metal layer thin film, and exposing, developing, etching, removing of the photoresist are performed by using a second mask, and thus, the gate electrode and the gate line pattern are formed.
Based on patterns formed by the second mask process, an ion doping to the source/drain region of the P-Si is performed by using the gate electrode above the channel region as a barrier layer. An ion doped region is formed at the source/drain region after the ion doping, after the ion doping ends, crystal lattices of the P-Si regularly crystallized are destroyed by the ion doping, in order to restore the crystal lattices of the P-Si, a annealing treatment is also needed and serves to reform the crystal lattices of the P-Si on the one hand and to diffuse doped ions on the other hand.
The third mask process: forming contact holes used to connect the P-Si in the source/drain region and a source/drain electrode.
A layer of interlayer insulating layer thin film is formed on patterns obtained after the above processes, and then, a layer of photoresist is coated on the interlayer insulating layer thin film, and exposing, developing, etching, removing of the photoresist are performed by using a third mask to form the contact holes.
The fourth mask process: forming the source/drain electrode and a data line pattern.
On patterns formed by the third mask process, a source/drain metal layer thin film is deposited, then the photoresist is coated on the source/drain metal layer thin film, and exposing, developing, etching, removing of the photoresist are performed by using a fourth mask to form the source/drain electrode and the data line pattern.
The fifth mask process: forming a through hole exposing a part of the source/drain electrode.
On patterns formed by the fourth mask process, a passivation layer thin film is deposited, and then a photoresist is coated exposing, developing, etching, removing of the photoresist are performed by using a fifth mask to form the through hole.
The sixth mask process: on patterns formed by the fifth mask process, a pixel electrode layer thin film is deposited, and then a photoresist is coated, exposing, developing, etching, removing of the photoresist are performed by using a sixth mask to form a pixel electrode pattern.
The seventh mask process: on patterns formed by the sixth mask process, a layer of protective layer thin film is deposited, and then a photoresist is coated, exposing, developing, etching, removing of the photoresist are performed by using a seventh mask to form a pixel edge protective layer pattern. This mask process is applicable to the LTPS AMOLED, and may not be used for the LTPS LCD.
The traditional technology for fabricating the LTPS thin film transistor (TFT) array substrate by using the 7-Mask process has a complex fabricating process and relatively more fabricating flows, and the fabricating cost is caused to be increased.